Balanced Ternary CPU ISA: Deep Dive into Non-Binary Compu...

*Analogue-Hermetic Ternary Research Core, v2.0* *Author: Skeome* Table of Contents 1. Overview 2. Balanced Ternary Fundamentals 3. Word Hierarchy 4. CPU Architecture 5. Instruction Encoding (9-9-9 Trinity Layout) 6. Opcode Zone Map 7. Instruction Reference - Data Movement - Arithmetic - Ternary (Kleene) Logic - Shift & Rotate - Compare & Branch - Debug & I/O - Hardware Receptor 8. Assembler Syntax 9. Two-Pass Assembler 10. Interactive Sandbox 11. Hardware Backends 12. Kleene Logic Gate Reference Overview Ternary-AL v2.0 is a balanced ternary CPU ISA running on a **Triple-word** (27-trit) architecture. Every instruction is exactly one Triple (27 trits), split into three 9-trit Trinity segments. The system bridges an analogue receptor layer (physical ADC/SPI/GPIO or stochastic simulation) with a software-defined ternary CPU, enabling research into three-valued logic, analogue-to-ternary sensing, and non-binary computing. Balanced Ternary Fundamentals Balanced ternary uses the digit set **{−1, 0, +1}**, written as **T**, **0**, **1** respectively. Symbol Value Meaning -------- ------- --------- T −1 Negative trit 0 0 Zero trit 1 +1 Positive trit A number in balanced ternary is the sum ∑ dᵢ × 3ⁱ where dᵢ ∈ {−1, 0, 1}. **Examples:** BT string (MST left) Decimal ---------------------- --------- 1 +1 T −1 10 +3 1T +2 T1 −2 1T01 +19 **Key identity:** Tritwise NOT (¬t = −t) equals arithmetic negation. There is no separate negation circuit. Word Hierarchy Name Power Trits Range ----------- ------- ------- ------- Trit 3⁰ 1 −1 to +1 Tryte 3¹ 3 −13 to +13 **Trinity** 3² **9** **−9,841 to +9,841** Triple 3³ 27 ±3,812,798,742,493 Tesseract 3⁴ 81 ±2.21 × 10³⁸ All registers hold one **Trinity** (9 trits). All instructions are one **Triple** (27 trits). CPU Architecture ┌─────────────────────────────────────────────────┐ │ Registers: R0..R9 (each 9 trits / one Trinity) │ │ R0 = constant Zero (writes silently discarded) │ │ R1..R9 = general purpose │ ├───────────────────────┬─────────────────────────┤ │ STATUS (1 trit) │ PC (integer, trit addr) │ │ Neg / Zero / Pos │ advances by 27 per instr│ ├───────────────────────┴─────────────────────────┤ │ Memory: flat array of Trit │ │ Default: 27 × 243 = 6,561 trits (243 instrs) │ │ Addressed by trit index (1-indexed) │ ├─────────────────────────────────────────────────┤ │ Receptor Interface (optional) │ │ ADS1115 / MCP3008 / GPIO / Serial / Simulated │ └─────────────────────────────────────────────────┘ **Status trit** is updated by most instructions to the sign of the result: - Pos (+1) if result > 0 - Zero (0) if result = 0 - Neg (−1) if result < 0 Branch instructions test this trit. Instruction Encoding Every instruction is 27 trits divided into three 9-trit **Trinity** segments: Trits 1 – 9 │ Segment A │ Opcode (±9841, zone-mapped) Trits 10 – 18 │ Segment B │ DST[10-12] SRC1[13-15] SRC2[16-18] Trits 19 – 27 │ Segment C │ Immediate (±9841) Register indices (DST, SRC1, SRC2) are packed into 3-trit Tryte fields, giving indices 0–9. The **immediate** (Segment C) is a full Trinity value (±9841), used for: - Literal constants (LOADI, ADDI, etc.) - Memory addresses (LOAD, STORE, etc.) - Jump targets (JMP, JEZ, etc.) - Hardware channel numbers (RECEP, QUERY_I2C, etc.) Opcode Zone Map Opcodes are scaled by 3⁶ = 729 into three logical zones: −9841 to −5001 │ System Control │ branches, shifts, Kleene extended, I/O −5000 to 5000 │ Arithmetic & Logic│ data movement, arithmetic, logic 5001 to 9841 │ Hardware Receptor │ ADC / SPI / GPIO / coherence Opcode Mnemonic Zone -------- ---------- ------ −9477 HALT System −9476 RESET System −8748 PRINT System −8747 DUMP System −8746 PRINTS System −8745 PRINTI System −8744 PRINTB System −7290 CMP System −7289 CMPI System −7288 MIN System −7287 MAX System −6561 JMP System −6560 JEZ System −6559 JNZ System −6558 JGT System −6557 JLT System −6556 JGEZ System −6555 JLEZ System −5832 LSHIFT System −5831 RSHIFT System −5830 LSHIFTN System −5829 RSHIFTN System −5828 ROTL System −5827 ROTR System −5103 TNOT System −5102 TNAND System −5101 TNOR System −5100 TXNOR System −5099 TIMP System −5098 TMUX System −5097 TMAJ System −5096 TCONS System −4374 TXOR A&L −4373 TXORI A&L −3645 TOR A&L −3644 TORI A&L −2916 TAND A&L −2915 TANDI A&L −2187 DIV A&L −2186 DIVI A&L −2185 MOD A&L −2184 MODI A&L −1458 MUL A&L −1457 MULI A&L −729 STORE A&L −728 STORER A&L −727 STOREI A&L 0 NOP A&L 729 LOAD A&L 730 LOADI A&L 731 LOADR A&L 1458 MOV A&L 1459 XCHG A&L 2187 ADD A&L 2188 ADDI A&L 2916 SUB A&L 2917 SUBI A&L 2918 NEG A&L 2919 ABS A&L 3645 INC A&L 3646 DEC A&L 3647 SIGN A&L 4374 SSET A&L 5103 RECEP HW 5104 SENSE HW 5105 SAMP_DB HW 5832 SETTH_P HW 5833 SETTH_N HW 5834 RCLEAR HW 5835 RSTAT HW 6561 QUERY_I2C HW 6562 WRITE_I2C HW 7290 QUERY_SPI HW 7291 WRITE_SPI HW 8019 GPIO_READ HW 8020 GPIO_WRITE HW 9477 COHERE HW 9478 ARRAY_N HW 9479 GAIN HW Instruction Reference Notation: Rd = destination register, Ra/Rb/Rc = source registers, imm = immediate integer or label. Operands are **space-separated** (no commas). All mnemonics are case-insensitive. Most instructions update **STATUS** to the sign of the result. Exceptions are noted. Data Movement Syntax Operation Notes -------- ----------- ------- LOAD Rd imm Rd = mem[imm] Reads 9-trit Trinity word at trit-address imm LOADI Rd imm Rd = imm Immediate directly into register; no memory access LOADR Rd Ra Rd = mem[Ra] Indirect: address is value of Ra STORE Rs imm mem[imm] = Rs Writes Rs to trit-address imm STORER Rs Ra mem[Ra] = Rs Indirect: address is value of Ra STOREI Rs imm mem[Rs] = imm Address in Rs, immediate value written MOV Rd Rs Rd = Rs Register copy XCHG Rd Rs Rd ↔ Rs Swap two registers; STATUS = new Rd Arithmetic All arithmetic results are **saturated** to ±9841 (the Trinity range). Syntax Operation Notes -------- ----------- ------- ADD Rd Ra Rb Rd = Ra + Rb Saturating ADDI Rd Ra imm Rd = Ra + imm SUB Rd Ra Rb Rd = Ra − Rb Implemented as Ra + (−Rb) via tritwise NOT SUBI Rd Ra imm Rd = Ra − imm MUL Rd Ra Rb Rd = Ra × Rb Saturating MULI Rd Ra imm Rd = Ra × imm DIV Rd Ra Rb Rd = Ra ÷ Rb Integer; div/0 sets STATUS=Neg, Rd unchanged DIVI Rd Ra imm Rd = Ra ÷ imm MOD Rd Ra Rb Rd = Ra mod Rb Sign follows dividend (BT convention) MODI Rd Ra imm Rd = Ra mod imm INC Rd Rd += 1 Saturating; operates on Rd in place DEC Rd Rd −= 1 Saturating; operates on Rd in place NEG Rd Rs Rd = −Rs Tritwise NOT == arithmetic negation (BT identity) ABS Rd Rs Rd = \ Rs\ Saturating SIGN Rd Rs Rd = sign(Rs) Full 9-trit Trinity: 000000001, 000000000, or 00000000T MIN Rd Ra Rb Rd = min(Ra, Rb) Numeric comparison MAX Rd Ra Rb Rd = max(Ra, Rb) Numeric comparison SSET Rs STATUS = sign(Rs) **No register write**; updates STATUS only Ternary (Kleene) Logic Operations are **tritwise** across all 9 trits. Kleene strong three-valued logic: Syntax Operation Rule -------- ----------- ------ TNOT Rd Rs Rd = ¬Rs T↔1, 0→0 TAND Rd Ra Rb Rd = Ra ∧ Rb min(a, b) per trit TANDI Rd Ra imm Rd = Ra ∧ imm TOR Rd Ra Rb Rd = Ra ∨ Rb max(a, b) per trit TORI Rd Ra imm Rd = Ra ∨ imm TXOR Rd Ra Rb Rd = Ra ⊕ Rb OR(AND(a,¬b), AND(¬a,b)) TXORI Rd Ra imm Rd = Ra ⊕ imm TNAND Rd Ra Rb Rd = ¬(Ra ∧ Rb) TNOR Rd Ra Rb Rd = ¬(Ra ∨ Rb) TXNOR Rd Ra Rb Rd = ¬(Ra ⊕ Rb) TIMP Rd Ra Rb Rd = Ra → Rb OR(¬Ra, Rb) TMUX Rd Ra Rb STATUS-implicit MUX Pos→Ra, Zero→Rb, Neg→¬Ra TMAJ Rd Ra Rb Rc Rd = majority(Ra,Rb,Rc) Rc index encoded in imm field TCONS Rd Ra Rb Rd = consensus(Ra,Rb) Pos if sum>1, Neg if sum<−1, else Zero **TMUX detail:** Reads the current STATUS trit and selects between Ra, Rb, and ¬Ra. This is the hardware-efficient ternary selector. **TMAJ detail:** The third operand register index is stored in Segment C (imm field), allowing three distinct sources. Shift & Rotate Shifts are zero-filling. Rotation wraps LST↔MST. Syntax Operation -------- ----------- LSHIFT Rd Rs Rd = Rs << 1 trit (LST becomes 0) RSHIFT Rd Rs Rd = Rs >> 1 trit (MST becomes 0) LSHIFTN Rd Rs Rn Rd = Rs << \ Rn\ trits RSHIFTN Rd Rs Rn Rd = Rs >> \ Rn\ trits ROTL Rd Rs rotate left 1 trit (LST wraps to MST) ROTR Rd Rs rotate right 1 trit (MST wraps to LST) LSHIFTN/RSHIFTN take the shift count from the **absolute value** of Rn. Compare & Branch All jump targets are **absolute trit addresses** (1-indexed). Each instruction is 27 trits, so instruction N starts at trit 1 + (N-1)×27. Syntax Condition Jumps to -------- ----------- ---------- CMP Ra Rb (sets STATUS = sign(Ra−Rb)) — CMPI Ra imm (sets STATUS = sign(Ra−imm)) — JMP imm always imm JEZ imm STATUS == Zero imm JNZ imm STATUS != Zero imm JGT imm STATUS == Pos imm JLT imm STATUS == Neg imm JGEZ imm STATUS != Neg (≥ 0) imm JLEZ imm STATUS != Pos (≤ 0) imm CMP and CMPI update STATUS but do not write any register. Debug & I/O Syntax Action -------- -------- PRINT Rd Print Rd as trit-string and decimal, e.g. R3 = 100T001T0 (42) PRINTI imm Print imm as decimal PRINTB Rd imm Print Rd in base imm; supported: 9, 12, 27, 60, 81 PRINTS Rd Print null-terminated trit string from mem[Rd]; each tryte is one char DUMP Print all R1..R9, STATUS, PC NOP No operation HALT Stop execution RESET Clear R1..R9, STATUS, PC=1; memory preserved RCLEAR Flush receptor history buffer and reset sample count Hardware Receptor The receptor layer bridges analogue/digital hardware to the CPU. Receptor opcodes are in the **Hardware Receptor zone** (5001–9841). Syntax Action -------- -------- RECEP Rd imm Sample receptor channel imm → Rd (single sample) SENSE Rd imm Take imm samples and majority-vote channel 0 → Rd SAMP_DB Rd Rd[LST] = current dead-band state (Zero if in dead-band) SETTH_P Rs Set positive threshold to Rs / 1000 volts SETTH_N Rs Set negative threshold to Rs / 1000 volts RSTAT Rd Rd = encoded status: n_channels + sample_count×10 QUERY_I2C Rd imm Read ADS1115 channel imm; voltage × 1000 → Rd WRITE_I2C Rs imm Write Rs to ADS1115 register imm QUERY_SPI Rd imm Read MCP3008 channel imm; voltage × 1000 → Rd WRITE_SPI Rs imm Write Rs to MCP3008 config register imm GPIO_READ Rd imm Read GPIO pin imm; trit state → Rd GPIO_WRITE Rs imm Write LST of Rs to GPIO pin imm COHERE imm Set simulated ξ = imm / 1000 (range 0..1000) ARRAY_N imm Set simulated array size N = imm GAIN Rd Rd = ξ²N² clamped to ±9841 **Threshold encoding:** SETTH_P/N operate on millivolt values. LOADI R1 750 then SETTH_P R1 sets the positive threshold to 0.750 V. **GPIO polarity:** GPIO_WRITE drives the pin HIGH for Pos, LOW otherwise. GPIO_READ returns Pos/Neg/Zero based on pin pair logic (pos_pin high and neg_pin low = Pos; neg_pin high = Neg; both equal = Zero). Assembler Syntax Basic Rules MNEMONIC ARG1 ARG2 ... ; optional comment LABEL: ; define a label at the current address - Operands are **space-separated** (not comma-separated) - Mnemonics and register names are **case-insensitive** - Everything after ; on a line is a comment - Blank lines are ignored Operand Types Type Format Examples ------ -------- --------- Register Rn where n = 0..9 R0 R4 R9 Immediate Decimal integer 42 -100 9841 Label ref Name string LOOP EXIT start Example Programs **Simple arithmetic:** asm ; R3 = R1 + R2 LOADI R1 10 LOADI R2 32 ADD R3 R1 R2 PRINT R3 HALT **Counting loop:** asm LOADI R1 0 ; counter LOADI R2 5 ; limit LOOP: PRINT R1 INC R1 CMP R1 R2 JLT LOOP ; jump back while R1 < R2 HALT **Ternary logic example:** asm LOADI R1 9 ; 000000100 in BT LOADI R2 -9 ; 00000T100 in BT TAND R3 R1 R2 TXOR R4 R1 R2 TNOT R5 R1 DUMP HALT **Reading from the receptor:** asm COHERE 750 ; ξ = 0.750 ARRAY_N 16 ; N = 16 SENSE R1 20 ; majority vote of 20 samples → R1 SIGN R2 R1 ; sign(R1) → R2 PRINT R2 HALT Two-Pass Assembler assemble_program(lines) processes a Vector{String}: **Pass 1 — Label collection:** - Strips comments, normalises whitespace - Lines ending in : define a label pointing to the current trit address - Labels are converted to uppercase and stored in a dictionary **Pass 2 — Code generation:** - Every non-label line is handed to parse_assembly_line(line, labels, pc) - Assembled instructions are 27 trits each - Label references in jump/branch targets resolve to their trit address **Return value:** AssemblyProgram with fields: - .code — Vector{Trit}, the assembled program - .labels — Dict{String,Int}, label→trit-address mapping **Loading and running:** julia prog = assemble_program(split(""" LOADI R1 7 LOADI R2 6 MUL R3 R1 R2 PRINT R3 HALT """, '\n')) cpu = CPU() load_program!(cpu, prog.code) run!(cpu) Interactive Sandbox Start with julia Balanced_Ternary_V2.jl and choose option 2–7 (or 1 for demo). At the T-AL> prompt, you can: - **Type any assembly instruction** to assemble and execute it immediately at the current PC - **Type a sandbox command** (listed below) Sandbox Commands Command Action --------- -------- run Run program until HALT or max_cycles step Execute one instruction reset Clear R1..R9, STATUS, PC=1; memory preserved monitor Show full CPU state (all regs, status, PC, next instr) status Show just STATUS trit and PC trace [on\ off] Toggle per-instruction trace (shows mnemonic and PC after each step) memdump ADDR LEN Dump LEN Trinity words (9 trits each) starting at trit-address ADDR convert N Display decimal N as balanced-ternary + all supported base encodings receptor Show receptor layer status: backend type, channels, sample counts, majority vote help Print the full reference card quit / exit Shut down the sandbox Inline Execution Behaviour When you type an assembly instruction at the prompt it is: 1. Assembled into a 27-trit instruction 2. Written into memory at the current PC 3. Executed immediately 4. PC advances by 27 trits This means sequential inline instructions build up a program in memory starting from PC=1. Use reset to clear PC and registers before re-running, or memdump to inspect what was written. Hardware Backends The receptor layer is selected automatically or by menu choice: Backend Hardware Channels Notes --------- ---------- ---------- ------- ADS1115Backend ADS1115 I²C ADC 4 16-bit; ±4.096 V PGA MCP3008Backend MCP3008 SPI ADC 8 10-bit; 0–3.3 V SerialBackend UART device 4 Expects space-separated floats per line GPIOBackend RPi GPIO (digital) N Each channel uses a positive + negative pin pair SimulatedBackend Pure Julia stochastic 8 Stochastic resonance model; operator coherence ξ Simulated Stochastic Resonance The simulated backend models an operator with coherence ξ ∈ [0,1] and array size N. Operator gain = ξ²N². Voltages are drawn from: v = signal_prob × N(0,1) + directed_signal × ξ × G × 0.1 Use COHERE and ARRAY_N instructions to tune the model at runtime. Kleene Logic Gate Reference Truth table for all binary gates (T = −1, 0 = 0, 1 = +1). XOR is defined as OR(AND(a,NOT(b)), AND(NOT(a),b)), IMP as OR(NOT(a),b), CONS as Pos if a+b > 1, Neg if a+b < −1, else Zero. a b AND OR XOR NAND NOR XNOR IMP CONS --- --- ----- ----- ----- ------ ----- ------ ----- ------ T T T T T 1 1 T 1 T T 0 T 0 0 1 0 0 1 0 T 1 T 1 1 1 T T 1 0 0 T T 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 T 0 1 0 1 T T 1 1 1 T T T 0 1 0 0 1 0 0 T 0 0 0 1 1 1 1 T T T 1 1 1 Unary NOT: T→1, 0→0, 1→T **XOR pattern:** gives 0 whenever either input is 0; for two non-zero inputs, 1 if they differ in sign (T,1 or 1,T), T if they are the same (T,T or 1,1). This is not modular addition — it is the Kleene exclusive-or derived from AND/OR/NOT. **IMP pattern:** IMP(a,b) = 0 only when a=Pos and b is not Pos (i.e. when the implication is falsified). IMP(0,b) = 0 for all b — indeterminate antecedent yields an indeterminate implication in Kleene's strong logic. *End of Ternary-AL v2.0 Reference*

This document provides a comprehensive reference for Ternary-AL v2.0, a balanced ternary CPU ISA designed with a Triple-word (27-trit) architecture and a focus on three-valued logic, analogue-to-ternary sensing, and non-binary computing. It details the balanced ternary fundamentals ({−1, 0, +1}), word hierarchy, CPU architecture, instruction encoding (9-9-9 Trinity Layout), opcode map, instruction reference across various categories (data movement, arithmetic, Kleene logic, shifts, branches, debug, I/O, hardware receptor), assembler syntax, and includes information on its two-pass assembler, interactive sandbox, hardware backends, and a Kleene logic gate reference table.